What is Heterogeneous Integration (HI)?

• HI is the process by which semiconductor components/circuits, with different functionality and/ or material systems, are physically and electrically combined together into a common 3-dimensional structure.

• Typically, chip interconnect and packaging is done utilizing a horizontal and multi-chip-module (MCM) format.
• Since interconnections between electrical components are vertical in an HI format or architechture, distances can be much shorter, resulting in significant performance enhancements. In fact, as the minimum gate dimension decreases much below 0.25 microns, numerous studies have shown that interconnect parasitics (and not minimum gate length) are the single most important impediment to increasing processor/access speed and reducing overall system power consumption.
• In all two-dimensional interconnect architectures, I/O (and ultimately system bandwidth) is limited by the number of connections that can be made along the perifery of the chip(s). In an HI architecture, interconnects can be made anywhere along the signal path, thus allowing for much higher interconnect density, and therefore, potentially higher bandwidth.

• If we wish to 3-dimensionally integrate two wafers (or chips), with disimilar electrical functions or material systems, both wafers are first front-side planarized, aligned and then covalently bonded to each other (front-side to front-side). The backside of wafer 2 (W2) is then thinned to 10-25 microns. High aspect ratio via holes are then formed where we wish to access wafer 1 (W1) and W2 metal layers. Metal is then deposited to form the electrical interconnection between W1 and W2. The process can be repeated to add additional wafers with different material and/or functionality.