Through Silicon Vias (TSVs):

R3 has focused on the manufacturing of reliable and dense TSVs since 2002.  Using maximum I/O connectivity as a driver, R3 focused on enabling 10 million connections per square centimeter; resulting in the first demonstration of sub-micron (180-900nm) diameter TSVs with depths up to 25 microns (1 mil).  Manufacturing of sub-micron TSVs is accomplished using a variety of sophisticated processing tools to etch via holes in silicon and fill them using Aluminum.  Etching of via holes is done fully in parallel (versus sequential laser ablation techniques) using high density plasma sources.  Furthermore, for sub-micron features, it is critical that the profile of the hole be free of notable topography. R3 developed the technique to simultaneously etch silicon while co-depositing a passivation layer of silicon dioxide.  This provides an optically smooth finish with electrical isolation from nearby conductors.







After forming the via hole array, a base barrier of titanium nitride is deposited using ionized Physical Vapor Deposition (PVD), commonly known as sputtering.  This provides both a physical barrier against aluminum absorption into the silicon and dislocation planes for the extrusion of aluminum.  Following the deposition of the liner material, an aluminum membrane is deposited under high vacuum and followed by a high pressure (20kpsi) extrusion of the aluminum into the holes for a complete fill.  Final processing of the vias consists of a metal Chemical Mechanical Polish (CMP) to remove any excess metal.  This sub-micron TSV capability was developed and matured by R3 engineers 13 years ahead of the ITRS roadmap for 3DI.