Projects / 3 Dimensional Integration

Project Overview

3-Dimensional Integration (3DI) is the vertical integration of thinned COTS components using through silicon vias (TSVs) for electrical connectivity through the periphery of the die.  3DI has the potential to dramatically increase the functionality in a given volume by minimizing the thickness of each layer to less than 25 microns (1 mil), or the thickness of a human hair.  Furthermore, by employing sub-micron through silicon vias widely parallel processing for high throughput data can be demonstrated.  Finally, given industry efforts to use 3DI to bridge technology nodes, superscalar architectures can be stacked to reduce on-chip latency, heat generation and power consumption.

Core Fabrication Technologies


3DI processing relies on the processing on bare or COTS depackaged die at the 150mm (6 inch) diameter wafer scale.  Wafer-scale processing helps reduce overall system fabrication cost by amortizing the production overhead across multiple systems.  After temporary bonding to a carrier wafer using advanced packaging techniques, modified die/substrate thinning processes are used to thin the die to 15-35 microns in thickness.  The thinned parts are then bonded to a permanent handle wafer iteratively using either covalent (chemically bonded)or
polymer (adhesive) wafer bonding processes to create a vertical stack of chips.
Following the formation of the base stack layer, standard semiconductor fabrication methods are used to route signals, using micron-scale wires, from the vertical interconnect point to the electric al contact pads on the periphery of the base chip.  After the routing is complete, the next layer of thinned die is bonded to form the next layer.  Then the vertical connections, called through silicon vias (TSVs) are formed to make the electrical connections between the layers.  This process can be repeated as needed to create iterative stacks.